Monthly Archives: October 2014


Explain the following with the help of a suitable diagram or an example: – Evaluation stack architecture 5m Dec2005

Explain the following with the help of a suitable diagram or an example. 

Evaluation stack architecture 5m Dec2005

A stack is a data structure that implements Last-In-First-Out (LIFO) access policy. You could add an entry of data (or value) to the stack with a PUSH (value) Function and remove an entry of data (or value) from the stack with a POP ( ) Function.

No explicit operands are used in ALU instructions, but one operand in PUSH (value) as parameter to be pushed on to the stack and In POP ( ) as return value to be popped from the stack.

Examples of such computers are Burroughs B5500/6500, HP 3000/70 etc.

 

On a stack machine “C = A + B” might be implemented as:

 

PUSH A
 
PUSH B
 
ADD // operator POP operand and PUSH result  (implicit on top of stack)
 
POP C

 

 

Stack Architecture: Pros and Cons

  •  Small instructions (does not need many bits to specify the operation).
  •  Compiler is easy to write.
  •  Lots of memory accesses required – everything that is not on the stack is in memory.

Thus, the result of which the machine performance is poor.

Explain the following with diagram or example:- Parameter passing using stack in 8086 assembly language 5m Dec2005

Explain the following with the help of a suitable diagram or an example:- Parameter passing using stack in 8086 assembly language 5m Dec2005

 Most HLLs use the stack to pass parameters because this method is fairly efficient. To pass parameters on the stack, push them immediately before calling the subroutine. The subroutine then reads this data from the stack memory and operates on it appropriately.

You could gain access to the parameters passed on the stack by removing the data from the stack (Assuming a near procedure call):

CallProc proc near
pop RtnAdrs
pop kParm
pop jParm
pop iParm
push RtnAdrs
.
.
.
ret
CallProc endp

 

There is, however, a better way. The 80×86’s architecture allows you to use the bp (base pointer) register to access parameters passed on the stack. This is one of the reasons the disp[bp], [bp][di], [bp][si], disp[bp][si], and disp[bp][di] addressing modes use the stack segment rather than the data segment. The following code segment gives the standard procedure entry and exit

code:

StdProc proc near
push bp
mov bp, sp
.
.
.
pop bp
ret ParmSize
StdProc endp

ParmSize is the number of bytes of parameters pushed onto the stack before calling the procedure. In the CallProc procedure there were six bytes of parameters pushed onto the stack so ParmSize would be six. Take a look at the stack immediately after the execution of mov bp, sp in StdProc.

 The best technique for parameter passing is through stack. It is also a standard technique for passing parameters when the assembly language is interfaced with any high level language. Parameters are pushed on the stack and are referenced using BP register in the called procedure. One important issue for parameter passing through stack is to keep track of the stack overflow and underflow to keep a check on errors. Let us see example, by using stack for parameter passing.

Solved program can be found on this link

http://cssimplified.com/assignments/write-a-simple-near-procedure-in-8086-assembly-language-that-receives-one-16-bit-number-as-parameter-value-on-the-stack-from-the-main-module-it-returns-0-if-the-upper-byte-of-the-number-is-0-else-re

The instruction MOV BP, SP transfers the contents of the SP to the BP register. Now BP is used to access any location in the stack, by adding appropriate offset to it. For example, MOV AX, [BP + 12] instruction transfers the word beginning at the 12th byte from the top of the stack to AX register. It does not change the contents of the BP register or the top of the stack. It copies the pushed value of AH and AL at offset 008Eh into the AX register. This instruction is not equivalent to POP instruction.

Stacks are useful for writing procedures for multi-user system programs or recursive procedures. It is a good practice to make a stack diagram as above while using procedure call through stacks. This helps in reducing errors in programming.

Example:

DATA SEGMENT
MSG DB “BIT RETURNED IS : $”
DATA ENDS

CODE SEGMENT
ASSUME DS:DATA,CS:CODE
START:
MOV AX,DATA
MOV DS,AX

MOV BX,0FFFH

LEA DX,MSG
MOV AH,9
INT 21H

PUSH BX

CALL CHECK

ADD DL,30H
MOV AH,2
INT 21H

MOV AH,4CH
INT 21H
CODE ENDS

CHECK PROC NEAR
POP AX
POP BX

AND BH,11110000B

MOV CL,4
ROL BH,CL

CMP BH,0
JE SKIP

MOV DL,1
JMP DONE
SKIP:
MOV DL,0
DONE:
PUSH AX
RET
CHECK ENDP

END START

What will be the values of select inputs, carry-in input and result of operation if the following micro-operations are performed? – IGNOU MCA Assignment 2014 – 15

MASTER OF COMPUTER APPLICATIONS
Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA (2)/012/Assign /2014-15
Maximum Marks : 100
Weightage : 25%

Assume that you have a machine as shown in section 3.2.2 of Block 3 having the micro-operations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8 bit registers and contains 0001 1100 and 0111 1110 respectively. What will be the values of select inputs, carry-in input and result of operation (including carry out bit) if the following micro-operations are performed? (For each micro-operation you may assume the initial value of R1 and R2 as given above).

(i) Addition of R1 and R2

(ii) Exclusive OR of R1 and R2

(iii)Shift left R2 once

(iv) Decrement R1

(i) Addition of R1 and R2

 

S3

S2

S1

S0

Ci

F

Micro-operation

Name

0

0

0

1

0

F=x+y

R ß R1 + R2

Addition

 

 

0 0 0 1 1 1 0 0
0 1 1 1 1 1 1 0
1 0 0 1 1 0 1 0

 

S3

S2

S1

S0

Ci

F

Micro-operation

Name

Value of Result R

0

0

0

1

0

F=x+y

R ß R1 + R2

Addition

1001 1010

Micro-Operation_01  

 (ii) Exclusive OR of R1 and R2

S3

S2

S1

S0

Ci

F

Micro-operation

Name

0

1

1

0

-

F=x+y

R ß R1 + R2

Exclusive OR

 

 

0 0 0 1 1 1 0 0
0 1 1 1 1 1 1 0
0 1 1 0 0 0 1 0

 

S3

S2

S1

S0

Ci

F

Micro-operation

Name

Value of Result R

0

1

1

0

-

F=x+y

R ß R1 + R2

Exclusive OR

0110 0010

 Micro-Operation_02

 (iii)Shift left R2 once

S3

S2

S1

S0

Ci

F

Micro-operation

Name

1

0

-

-

-

F=Shl(x)

R ß Shl(R2)

Shift left

 

 

0 1 1 1 1 1 1 0
1 1 1 1 1 1 0 0

 

S3

S2

S1

S0

Ci

F

Micro-operation

Name

Value of Result R

1

0

-

-

-

F=Shl(x)

R ß Shl(R2)

Shift left

1111 1100

Micro-Operation_03

(iv) Decrement R1

S3

S2

S1

S0

Ci

F

Micro-operation

Name

0

0

-

-

-

F=x-1

R ß R1 - 1

Decrement

 

 

0 0 0 1 1 1 0 0
0 0 0 1 1 0 1 1

 

S3

S2

S1

S0

Ci

F

Micro-operation

Name

Value of Result R

0

0

-

-

-

F=x-1

R ß R1 - 1

Decrement

0001 1011

 

Micro-Operation_04

Explain how overlapped register window can be implemented for procedure calls. Explain the process of parameter passing for the subroutine call on this machine? – IGNOU MCA Assignment 2014 – 15

MASTER OF COMPUTER APPLICATIONS
Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA (2)/012/Assign /2014-15
Maximum Marks : 100
Weightage : 25%

Assume that a RISC machine has 64 registers out of which 16 registers are reserved for the Global variables. This machine has been designed to have 8 registers for storing two input parameters, two output parameters and four local variables for a single function. Explain with the help of a diagram, how the overlapped register window can be implemented in this machine for procedure calls. Explain the process of parameter passing for the subroutine call on this machine.

 

Assumptions:

Register file contains 64 registers. Let them be called by register number 0 – 63.

The table shows the use of registers: when there is call to function A (fA) which calls function B (fB) and function B calls function C (fC).

Overlapped_reg_window_01

 

Registers Nos. Used for

0 – 15

(16 Registers)

Global variables required by fA, fB, and fC Function A Function B Function C

16 – 21

(6 Registers)

Used by parameters of fC that may be passed to next call Temporary variables of function C

22 – 29

(8 Registers)

Used for local variable of fC Local variables offunction C

30 – 35

(6 Registers)

Used by parameters that were passed from fB à fC Temporary variables of function B Parameters of function C

36 – 43

(8 Registers)

Local variables of fB Local variables of function B

44 – 49

(6 Registers)

Parameters that were passed from fA to fB Temporary variables of function A Parameters of function B

50 – 57

(8 Registers)

Local variable of fA Local variables of function A

58 – 63

(6 Registers)

Parameter passed to fA Parameters of function A

This window consists of:

  • Global registers which are shareable by all functions.
  • Parameters registers for holding parameters passed from the previous function to the current function. They also hold the results that are to be passed back.
  • Local registers that hold the local variables, as assigned by the compiler.
  • Temporary registers: They are physically the same as the parameter registers at the next level. This overlap permits parameter passing without the actual movement of data.

The register buffer is filled as function A called function B, function B called function C, function C called function D. The function D is the current function. The current window pointer (CWP) points to the register window of the most recent function (i.e. D). Any register references by a machine instruction is added with the contents of this pointer to determine the actual physical registers. On the other hand the saved window pointer identifies the window most recently saved in memory. This action will be needed if a further call is made and there is no space for that call. If function D now calls function E arguments for function E are placed in D’s temporary registers indicated by D temp and the CWP is advanced by one window.

Circular_Buffer_window

If function E now makes a call to function F, the call cannot be made with the current status of the buffer, unless we free space equivalent to exactly one window. This condition can easily be determined as current window pointer on incrementing will be equal to saved window pointer.  Now, we need to create space. The simplest way will be to swap FA register to memory and use that space. Thus, an N window register file can support N –1 level of function calls.

Write and explain the sequence of micro-operations that are required to fetch and execute this instruction? – IGNOU MCA Assignment 2014 – 15

MASTER OF COMPUTER APPLICATIONS
Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA (2)/012/Assign /2014-15
Maximum Marks : 100
Weightage : 25%

A hypothetical 16 bit machine has PC, AC, MAR, IR, DR and Flag registers (You may assume the roles of these registers same as that are defined in general for a von Neumann machine). The instructions of this machine contain only one operand address which is a memory operand. On execution, the memory operand is first brought into the DR register. The second operand, if required, can be stored in AC register and the result of the operation is also stored in the AC register, if needed. The machine has the following instruction

STORE memAddress    // this instruction result in storage of the content of AC register into the memory location specified by memAddress.

Write and explain the sequence of micro-operations that are required to fetch and execute this instruction Make and state suitable assumptions, if any.

The instruction execution using the micro-operations requires:

  • Instruction fetch: fetching the instruction from the memory.
  • Instruction decode: decode the instruction.
  • Operand address calculation: find out the effective address of the operands.
  • Execution: execute the instruction.
  • Interrupt Acknowledge: perform an interrupt acknowledge cycle if an interrupt request is pending.Seq_Micro_Operations_01

     

    Instruction fetch:

    Transfer the address of PC to MAR. (Register Transfer) MAR ß PC
    MAR puts its contents on the address bus for main and issues a memory read signal. The word so read is placed on the data bus where it is accepted by the Data register.The PC is incremented by one memory word length to point to the next instruction in sequence. DR ß (MAR), 

     

    PCß PC +1

    The instruction is transferred from data register to the Instruction register processing. IR ß DR

     

    Instruction Decode: The Control Unit determines the operation that is to be performed and the addressing mode of the data.

     

    Operand Address Calculation: (In case of direct addressing)

    Transfer the address portion of instruction is the direct address so no further calculation needed. IR (Address) and DR (Address) contain the Effective address.

     

    Operand Address Calculation: (In case of indirect addressing)

    Transfer the address bits of instruction to the MAR. This transfer can be achieved using DR, as DR and IR at this point of time contain the same value. (Register Transfer) MAR ß DR (Address)
    Perform a memory read operation as done in fetch cycle and the desired address of the operand is obtained in the DR. (Memory Read) DR ß (MAR)
    Transfer the address part so obtained in DR as the address part of instruction. (Register Transfer) Thus, the indirect address is now converted to direct address or effective address. IR (Address) ß DR (Address)

     

    Execution:

    Transfer the address portion of the instruction to the MAR. (MemAddress transfer) MAR ß MemAddress
    Store the AC register to Memory Address in MAR.   (MAR) ß AC

     

    Interrupt Processing:

    Transfer the contents of PC to DR DR ß PC
    Place the address of location, where the return address is to be saved, into MAR. MAR ß Address of location for saving return address.
    Store the contents of PC in the memory using DR and MAR. (Memory write) Transfer the address of the first instruction of interrupt servicing routine to the PC. (MAR) ßDRPC ß address of the first instruction interrupt service programs

Assume that a new machine has been developed. Give justification of the selection of every addressing mode? – IGNOU MCA Assignment 2014 – 15

MASTER OF COMPUTER APPLICATIONS
Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA (2)/012/Assign /2014-15
Maximum Marks : 100
Weightage : 25%

Assume that a new machine has been developed. This machine has 64 general purpose registers of 64 bits each. Out of these 64 registers, 32 registers are used as stack for subroutine calls. The machine has 1 GB main memory with memory word size of 64 bits. The Instructions of this machine is only one memory word. An instruction of the machine consists of opcode – 6 bits, addressing mode specification – 2 bits and remaining bits for specifying the operand addresses. An ADD instruction on this machine has a fixed opcode 110011. The four possible addressing modes for the ADD instruction are coded using the 2 bit addressing mode field. Each ADD instruction involves three operands with at least one of the operand as register operand. Design four ADD instructions, involving at least four different types of addressing modes. Give justification of the selection of every addressing mode

 

Total general purpose registers = 64

All Register equal size = 64 bits

Registers used as stack for subroutine calls = 32

Main memory = 1 GB

Memory word size = 64 bits

Instructions size = one memory word = 64 bits

Opcode = 6 bits

Addressing mode = 2 bits

Remaining bits = operand addresses

An ADD instruction has a fixed opcode = 110011

Each ADD instruction involves = 3 operands (with at least 1 as register operand)

 

Design four ADD instructions, involving at least four different types of addressing modes. Give justification of the selection of every addressing mode

 

Please note the following points:

  • The opcode size is 6 bits. So, in general it will have 26 = 32 operations.
  • There is three operand address machine.
  • There are two bits for addressing modes. Therefore, there are 22 = 4 different addressing modes possible for this machine.
  • The last field (8 – 64 bits = 56 bits) here is the operands or the addresses of operands field.

 

Addressing Mode = 2 bits

   Instruction_Format_01

An ADD instruction has a fixed opcode = 110011

Each ADD instruction involves = 3 operands (with at least 1 as register operand)

 

Since One register operand has to be involved in all Addressing modes, so we have to use first operand as Register for all modes and this will be common for all.

Instruction_Format_02

IMMEDIATE addressing mode:

Instruction_Format_03

ADD R 12 13                              R = 12 + 13

 

In case of immediate operand the maximum size of the unsigned operand would be 225

DIRECT addressing mode:

Instruction_Format_04

ADD R A B                                 R = A + B

 

In case it is an address of operand in memory, then the maximum physical memory size supported by this machine is 225 = 32 MB.

REGISTER addressing mode:

Instruction_Format_05

ADD R1 R2  R3                             R1 = R2 + R3

 

There are 64 general purpose registers. Therefore, there is 64 = 26 (6-bits for Register address)

REGISTER INDIRECT addressing mode:

Instruction_Format_06

ADD R1 R2 R3                              R1 = R2  + R3

ADD R1 (R2 ) (R3 )                       R1 = (R2 ) + (R3 )

ADD R A B                                 R = A + B

 There are 64 general purpose registers. Therefore, there is 64 = 26(6-bits for Register address)

 

Total Selected Addressing Modes:

00 - IMMEDIATE addressing mode

01 - DIRECT  addressing mode

10 - REGISTER addressing mode

11 - REGISTER INDIRECT addressing mode

What is rotational latency in the context of disk access time? – IGNOU MCA Assignment 2014 – 15

MASTER OF COMPUTER APPLICATIONS
Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA (2)/012/Assign /2014-15
Maximum Marks : 100
Weightage : 25%

What is rotational latency in the context of disk access time? Assume that the disk rotates at 6000 rpm; each track of the disk has 16 sectors; data transfer rate of the disk is 64 MB/second; and average seek time of disk is10 millisecond. Calculate the average access time for the disk.

Disk Rotation Speed = 6000 rpm

Sectors per Track = 16 sectors

Data transfer rate = 64 MB/second

Average seek time = 10 millisecond

 

Convertion is Shown Below:

Rpm_Covert

 

Rotational latency = Average seek time + Average Rotational delay + Transfer time + Controller Overheads

 

Average seek time = 10 millisecond (given)

 

Calculate

Average Rotational delay = ½ Time of Rotation in milliseconds

 

Average Rotational delay = ½ * (60/6000) *1000 millisecond

= ½ * 10 millisecond

= 5 millisecond

Calculate

Transfer time = Block size / Transfer rate

Block size =? (Not Mentioned)

Assume = 1 KB per 1 sector

So 16 sector = 16 KB

Transfer time = (16 KB / 64 MB/sec)

= (16 / 64) millisecond

= 0.25 millisecond

 

Note:-  Controller Overheads (optional) not using it For Now.

 

Rotational latency = Average seek time + Average Rotational delay + Transfer time

Rotational latency = 10 millisecond + 5 millisecond + 0.25 millisecond

= 10 + 5 + 0.25 millisecond

= 15.25 millisecond.

A computer has 512 words RAM with a word size of 32 bits and a cache memory of 8 Blocks with block size of 64 bits – IGNOU MCA Assignment 2014 – 15

MASTER OF COMPUTER APPLICATIONS
Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA (2)/012/Assign /2014-15
Maximum Marks : 100
Weightage : 25%

A computer has 512 words RAM with a word size of 32 bits and a cache memory of 8 Blocks with block size of 64 bits. Draw a diagram to show the address mapping of RAM and Cache, if

(i)                Direct cache mapping is used

(ii)             Associative cache mapping is used, and

(iii)           Two way set associative mapping scheme is used.

Main memory Size = 512 Words

Main Memory word size = 32 bits

Cache Memory Size = 8 Blocks

Cache Memory Block size = 64 bits

⇒1 Block of Cache = 2 Words of RAM

⇒ Total number of possible Blocks in Main Memory = 512/8 = 64 block

 

Mapping01

 

Associative Mapping:

The block can be anywhere in the cache.

Direct Mapping:

Size of Cache = 8 blocks

Location of Block 12 in Cache = 12 modulo 8 = 4

2 Way set associative mapping:

Number of blocks in a set = 2

Number of sets = Size of Cache in blocks / Number of blocks in a set

= 8 / 2 = 4

Block 12 will be located anywhere in (12 modulo 4) set, that is set 0.

A RAM has a capacity of 1024K having the word size of 64 bits – IGNOU MCA Assignment 2014 – 15

MASTER OF COMPUTER APPLICATIONS

Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA (2)/012/Assign /2014-15
Maximum Marks : 100
Weightage : 25%

RAM32x4

 

A 32 × 4 RAM means that RAM has 32 words,

5 address lines (25 = 32), and 4 bit data word size.

We can represent a RAM using 2A×D,

Where

A-> Number of address lines

D -> Number of Data lines

The 32 × 4 RAM circuit where 5 × 32 bit decoder is used

The 4 bit data input come from input buffer

The 4-bit data output is stored in output buffer

 

A RAM has a capacity of 1024K having the word size of 64 bits and supports only word addresses.

(i)                How many data input and output lines does this RAM need? Explain your answer.

Ans:  Data input and Data output lines are equal and of word size, Hence Ram will need 64 Data lines

 

(ii)             How many address lines will be needed for this RAM? Explain.

Ans:  Convert 1024K to 2A format 1024K/64

AddLines1

We can represent a RAM using 2A × D = 214 × 64 RAM Hence Address lines are 14 Address lines.