# Monthly Archives: November 2014

## Represent the following numbers in IEEE-754 floating point single precision number format: 4m Dec2005

Represent the following numbers in IEEE-754 floating point single precision number format:           4m Dec2005

(i)                 1011.1001

(ii)                -0.0011001

Single Precision

S stands for Sign (white color)

E stands for Exponent (yellow color)

N stands for Number (also called Mantissa or Significand) (green color)

0this Sign bit (1 bit)

1st to 8this Exponent bits (7 bits)

9thto 31this Exponent bits (24 bits)

Double Precision

S stands for Sign (white color)

E stands for Exponent (yellow color)

N stands for Number (also called Mantissa or Significand) (green color)

0this Sign bit (1 bit)

1st to 11this Exponent bits (10 bits)

12thto 63this Exponent bits (53 bits)

(i)                 1011.1001

Since number is a positive number

Sign bit is: 0

 0

Now let’s work on Mantissa part

First of all convert Binary number to Exponent Form

1011.1001 Will be 1.0111001 * 23

Take 0111001 as Significand

Significand number = (0111001)2

Significand bits are:

 0 1 1 1 0 0 1

Fill the Significand in the beginning

Rest all fills it with 0’s

We will have

Significand bits are:

 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

+3 is the Exponent

So we have to subtract it with 127

Exponent = 127+3=130

Exponent number (130)10 = (10000010)2

Exponent bits are:

 0 0 0 0 0 1 0

Note: we have to discard overflow bit since we have only 7 bits

(ii)               -0.0011001

Since number is a negative number

Sign bit is: 1

 1

Now let’s work on Mantissa part

First of all convert Binary number to Exponent Form

0.0011001 Will be 1.1001 * 2-3

Take 1001 as Significand

Significand number = (1001)2

Significand bits are:

 1 0 0 1

Fill the Significand in the beginning

Rest all fills it with 0’s

We will have

Significand bits are:

 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

-3 is the Exponent

So we have to subtract it with 127

Exponent = 127-3=124

Exponent number (124)10 = (1111100)2

Exponent bits are:

 1 1 1 1 1 0 0

## Explain the micro-instruction encoding methods with the help of suitable diagrams 10m Dec2005

Explain the micro-instruction encoding methods with the help of suitable diagrams. If a machine has a very large number of instructions and registers, which of the two encoding methods is preferred? 10m Dec2005

The characteristics of highly encoded and unencoded micro-instructions:-

Unencoded micro-instructions

•  One bit is needed for each control signal; therefore, the number of bits required in a micro-instruction is high.
•  It presents a detailed hardware view, as control signal need, can be determined.
•  Since each of the control signals can be controlled individually, therefore these micro-instructions are difficult to program. However, concurrency can be exploited easily.
•  Almost no control logic is needed to decode the instruction as there is one to one mapping of control signals to a bit of micro-instruction. Thus, execution of micro-instruction and hence the micro-program is faster.
•  The unencoded micro-instruction aims at optimising the performance of a machine.

Highly Encoded micro-instructions

•  The encoded bits needed in micro-instructions are small.
•  It provided an aggregated view that is a higher view of the CPU as only an encoded sequence can be used for micro-programming.
•  The encoding helps in reduction in programming burden; however, the concurrency may not be exploited to the fullest.
•  Complex control logic is needed, as decoding is a must. Thus, the execution of a micro-instruction can have propagation delay through gates. Therefore, the execution of micro-program takes a longer time than that of an unencoded micro-instruction.
•  The highly encoded micro-instructions are aimed at optimizing programming effort.

In most of the cases, the design is kept between the two extremes. The LSI 11 (highly encoded) and IBM 3033 (unencoded) control units are close examples of these two approaches.

If a machine has a very large number of instructions and registers, then we can prefer highly encoding methods of micro-instructions.

## Find out the errors, if any, in the following 5m Dec2005

Find out the errors, if any, in the following, and               5m Dec2005

(i)                 CMP AX, BX

No error

since two register operand are allowed for comparison in the permutations shown below.

(ii)               IDlV AX, CH

IDIV works or allows one parameter only and it can either be register or memory only as shown below.

corrected instruction will be IDIV CH

Errors shown while compiling:-

(1) illegal instruction: IDlV AX, CH or wrong parameters.

(0) not enough instructions…

(0) should be at least 1 instruction outside macro or before the ‘END’ directive

(iii)             DEC AL

No error

since one register operand are allowed for decremented value in the permutations shown below.

(iv)             AAA AX, BX

AAA works or allows no parameters as shown below.

corrected instruction will be AAA

Errors shown while compiling:-

(1)   illegal instruction: AAA AX, BX or wrong parameters.

(0)   not enough instructions…

(0) should be at least 0 instruction outside macro or before the ‘END’ directive

(v)               XCHG WORD1, WORD2

XCHG works with three permutations shown below in the table. The above permutation memory memory is not allowed.

corrected instruction will be MOV AX, WORD1

XCHG AX, WORD2

Errors shown while compiling:-

(1) wrong parameters: XCHG  WORD1, WORD2

## Design a decade counter using D-flipflop. Show all the steps involved 10m Dec2005

Design a decade counter using D-flipflop. Show all the steps involved 10m Dec2005

A BCD counter follows a sequence of ten states and returns to 0 after the count of 9. These counters are also called decade counters. This type of counter is useful in display applications in which BCD is required for conversion to a decimal readout.

 Present State Next State Flip-Flops Inputs A B C D A B C D DA DB DC DD 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0

There are 4 flip-flop inputs for decade counter i.e. A, B, C, D. The next state of flip-flop is given in the table. JA & KA indicates the flip flop input corresponding to flip-flop-A. This counter requires 4-flip-flops.

From this the flip flop input equations are simplified using K-Maps as shown below. The unused minterms from 1010 through 1111 are taken as don’t care conditions (X).

K-Map for Da is:

K-Map for Db is:

K-Map for Dc is:

K-Map for Dd is:

Thus, the simplified input equations for BCD counter are:

Da = BCD + A|D

Db = |BCD + B|C + B|D

Dc = |A|CD + C|D

Dd = |D

The logic circuit can be made with 4 D flip flops, 3 OR gates & 7 AND gates

## What is an interrupt? Explain each of the conditions under which an interrupt occurs 5m Dec2005

What is an interrupt? Explain each of the conditions under which an interrupt occurs 5m Dec2005

Interrupt

An interrupt is an external signal that occurs due to an exceptional event. It causes interruption in the execution of current program of CPU. An interrupt may be generated by a number of sources, which may beeither internal or external to the CPU.

When an interrupt occurs, it is acknowledged by the CPU, which executes an interrupt cycle which causes interruption of currently executing program, and execution of interrupt servicing routine (ISR) for that interrupt.

## Explain the working of the instruction pipelining, with the help of a diagram 5m Dec2005

Explain the working of the instruction pipelining, with the help of a diagram 5m Dec2005

INSTRUCTION PIPELINING

To extract better performance instruction execution can be done through instruction pipeline. The instruction pipelining involves decomposing of an instruction execution to a number of pipeline stages.

Some of the common pipeline stages can be instruction fetch (IF), instruction decode (ID), operand fetch (OF), execute (EX), store results (SR).

An instruction pipe may involve any combination of such stages. A major design decision here is that the instruction stages should be of equal execution time. The reason why it should be is,

A pipeline allows overlapped execution of instructions. Thus, during the course of execution of an instruction the following may be a scenario of execution.

A pipeline allows overlapped execution of instructions. Thus, during the course of execution of an instruction the following may be a scenario of execution.

Please note the following observations about the above figure:

•  The pipeline stages are like steps. Thus, a step of the pipeline is to be complete in a time slot. The size of the time slot will be governed by the stage taking maximum time. Thus, if the time taken in various stages is almost similar, we get the best results.
•  The first instruction execution is completed on completion of 5th time slot, but afterwards, in each time slot the next instruction gets executed. So, in ideal conditions one instruction is executed in the pipeline in each time slot.
•  After the 5th time slot and afterwards the pipe is full. In the 5th time slot the stages of execution of five instructions are:

SR (instruction 1) (Requires memory reference)

EX (instruction 2)          (No memory reference)

OF (instruction 3) (Requires memory reference)

ID (instruction 4)           (No memory reference)

IF (instruction 5)  (Requires memory reference)

## In RAID levels, explain the features of those levels which have poor I/O request rate (read/write) 5m Dec2005

In RAID levels, explain the features of those levels which have poor I/O request rate (read/write) 5m Dec2005

Redundancy of data industrial standard, which exists for multiple-disk database schemes, is termed as RAID, i.e., Redundant Array of Independent Disks.

The basic characteristics of RAID disks are:

•  Operating system considers the physical disks as a single logical drive.
•  Data is distributed across the physical disks.
•  In case of failure of a disk, the redundant information (for example, the parity bit) kept on redundant disks is used to recover the data.

 RAID Level Category Features I/O Request Rate (Read /write) Typical Application 2 Parallel Access a) All member disks participate in the execution of every I/O request by synchronising the spindles of all the disks to the same position at a time. b) The strips are very small, often a single byte or word. c) Redundancy via hamming code which is able to correct single-bit errors and detect double-bit errors. Poor Commercially not useful. 3 Parallel Access a) Employs parallel access as that of level 2, with small data strips. b) A simple parity bit is computed for the set of data instead of an errorcorrecting code in case a disk fails. Poor Large I/O request size application, such as imaging CAD 6 Independent access a) Also called the P+Q redundancy scheme is much like level 5, but stores extra redundant information to guard against multiple disk failures. b) P and Q are two different data check algorithms. One of the two is the exclusive-or calculation used in level 4 and 5. The other one is an independent data check algorithm. Excellent/ poor Application requiring extremely high availability

## Represent the number (-26.5)10 as a floating point binary number with 24 bits. The normalized fraction mantissa has 16 bits and the exponent has 8 bits 5m Dec2005

Represent the number (-26.5)10 as a floating point binary number with 24 bits. The normalized fraction mantissa has 16 bits and the exponent has 8 bits. Make and state suitable assumptions, if any 5m Dec2005

First of all draw the 24 bits precision representations

S stands for Sign (white color)

E stands for Exponent (yellow color)

N stands for Number (also called Mantissa or Significand) (green color)

Then to represent we have (-26.5)10 using 24 bits precision representations

Since number is a negative number

Sign bit is: 1

 1

Now let’s work on Mantissa part

Convert 26 into binary form i.e 11010

Remaining is fraction part 0.5

Now we multiply fraction value with 2 till we get whole number 1 at the end.

We reach 1 so we stop

Write number from top to bottom

We get 0.5 = 1

Number (-26.5)10 = (11010.1)2

Convert Binary number to Exponent Form

11010.1 Will be 1.10101 * 24

Take 11010 as Significand

Significand number = (11010)2

Significand bits are:

 1 1 0 1 0

Fill the Significand in the beginning

Rest all fills it with 0’s

We will have

Significand bits are:

 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0

+4 is the Exponent

So we have to subtract it with 127

Exponent = 127+4=130

Exponent number (130)10 = (10000010)2

Exponent bits are:

 0 0 0 0 0 1 0

Note: we have to discard overflow bit since we have only 7 bits

## RegisterA holds the 8-bits 11011001. Determine the B operand and the logic micro-operation to be performed in order to change the value in A to: 5m Dec2005

RegisterA holds the 8-bits 11011001. Determine the B operand and the logic micro-operation to be performed in order to change the value in A to:  5m Dec2005

1. 01101101
2. 11111101

First refer the table for Logic micro-operations  which can be applied.

R1:- 1 0 1 0        (initial value)          R2:- 1 1 0 0        (initial value)

 Operation name What is the operation? Explanation Example Selective Set Sets those bits in Register R1 for which the corresponding R2 bit is 1. The value 1110 suggests that selective set can be done using logic OR micro-operation.Please note that all those bits of R1, for which we have 0 bit in R2, have remained unchanged. The bits in R1 which need to be set selectively must have the corresponding R2 bits as 1. 1010 = R11100 = R21110 Selective Clear Clear those bits in register R1 for which corresponding R2 bits are 1. The R1 value after the operation is 0010which suggests that Corresponding micro-operation is R1 AND Compliment R2 1010 = R11100 = R20010 Selective Complement Complement those bits in register R1 for which the corresponding R2 bits are 1. The R1, value 0110 after the operation suggests that the selective complement can be done using exclusive – OR micro-operation.The bits in R1 which need to be complemented selectively must have the corresponding R2 bits as 1. 1010 = R11100 = R20110 Mask Operations Clears those bits in Register R1 for which the corresponding R2 bits are 0. The R1 value after the operation is 1000 which suggests that the mask operation can be performed using AND micro-operation.However, the bits in R1 which are cleared or masked correspond to the bits on R2 having a 0 value. The mask operation is preferred over selective clear as most of the computers provide AND micro-operation while the micro-operation required for implementing selective clear is normally not provided in computers 1010 = R11100 = R21000 Clear Clear all the bits Implemented by taking exclusive OR with the same number. The exclusive OR, thus, can also be used for checking whether two numbers are equal or not. 1010 = R11010 = R10000 Insert For inserting a new value in a bit. It is a two-step process: Step 1: Mask out the existing bit valueStep 2: Insert the bit using OR micro-operation with the bits which are to be inserted. This is a two-step process. Example:Say contents of R1 = 0011 1011Suppose, we want to insert 0110 in place of left most 0011 then:0011 1011 (R1 before)0000 1111 (R2 for masking) Perform AND operation (mask) 0000 1011 (R1 after) Now insert: 01100000 (R2 for insertion) Perform OR operation 0110 1011 R1 after insert 0011 1011 = R1we want to insert 0110 in place of left most 00110110 1011 = R1

Result may be different for all. You just apply the answer which comes to your mind first.

1.             A        1101 1001

B         1010 0100       (Selective Complement)

—————

0110 1101

2.           A        1101 1001

B      0011 1100       (Selective Set)

—————

1111 1101

## Construct 16-to-1 line multiplexer with two 8-to-1 line multiplexers and one 2-to-1 line multiplexer. Makes suitable assumptions, if any 5m Dec2005

Construct 16-to-1 line multiplexer with two 8-to-1 line multiplexers and one 2-to-1 line multiplexer. Makes suitable assumptions, if any 5m Dec2005

Multiplexer

Multiplexer is one of the basic building units of a computer system which in principle allows sharing of a common line by more than one input lines. It connects multiple input lines to a single output line. At a specific time one of the input lines is selected and the selected input is passed on to the output line.

Relation between multiple Input lines and Selection lines

Input lines 16 = 24 i.e. 4 Selection lines

Input lines will be I0 - I15

Selection lines will be S0 - S3

Block Diagram:

Constructed Diagram:

The diagram will be same as of the block diagram of 16-to-1 line multiplexer in which 8-to-1 line multiplexer Selection lines will be S0 - S2and S3will be connected to 2-to-1 line multiplexer Selection and First 8-to-1 line multiplexer Input lines will be I0 - I7and Second8-to-1 line multiplexer Input lines will be I8 - I15

Write an assembly program to convert a 4digit BCD number to its binary equivalent 5m Dec2005