# Monthly Archives: March 2016

## Draw the state table and the logic circuit for a 3-bit binary counter using D flipflop. 5m Jun2008

Draw the state table and the logic circuit for a 3-bit binary counter using D flipflop. 5m Jun2008

Binary counter

A digital circuit which has a clock input and a number of count outputs which give the number of clock cycles. The output may change either on rising or falling clock edges. The circuit may also have a reset input which sets all outputs to zero when asserted. The counter may be either a synchronous counter or a ripple counter.

 Present State Input Next State Flip-Flops Inputs A B C X A B C DA DB DC 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0

There are 3  inputs for binary counter i.e. A, B, C. The next state of flip-flop is given in the table. DA indicates the flip flop input corresponding to flip-flop-A. This counter requires 3-flip-flops.

K-Map for Da is:

K-Map for Db is:

K-Map for Dc is:

A sequential circuit is specified by a time sequence of external inputs, external outputs and internal flip-flop binary states. Thus firstly, a state table and state diagram is used to describe behaviour of the circuit

Thus, the simplified input equations for binary counter are:

DA = |ABCX + A|C+ AX + A|B

DB = |BCX + B|C + B|X

DC = |CX + C|X

The logic circuit can be made with 3 D flip flops, 3 OR gates & 9 AND gates

## Give block diagram of DMA controller. How does the CPU initialize the DMA transfer? 5m Jun2008

Give block diagram of DMA controller. How does the CPU initialize the DMA transfer? 5m Jun2008

Device Controller

A device controller need not necessarily control a single device. It can usually control multiple I/O devices. It comes in the form of an electronic circuit board that plugs directly into the system bus, and there is a cable from the controller to each device it controls. The cables coming out of the controller are usually terminated at the back panel of the main computer box in the form of connectors known as ports.

The Figure 2 below illustrates how I/O devices are connected to a computer system through device controllers. Please note the following points in the diagram:

• • Each I/O device is linked through a hardware interface called I/O Port.
• • Single and Multi-port device controls single or multi-devices.
• • The communication between I/O controller and Memory is through bus only in case of Direct Memory Access (DMA), whereas the path passes through the CPU for such communication in case of non-DMA.

Using device controllers for connecting I/O devices to a computer system instead of connecting them directly to the system bus has the following advantages:

• • A device controller can be shared among multiple I/O devices allowing many I/O devices to be connected to the system.
• • I/O devices can be easily upgraded or changed without any change in the computer system.
• • I/O devices of manufacturers other than the computer manufacturer can be easily plugged in to the computer system. This provides more flexibility to the users in buying I/O devices of their choice.

(c) What is instruction pipelining? Explain the working of instruction pipelining in RISC processor. 5

## Explain briefly the working of two-pass assembler. 5m Jun2008

Explain briefly the working of two-pass assembler. 5m Jun2008

Two-pass assembler: Assemblers typically make two or more passes through a source program in order to resolve forward references in a program. A forward reference is defined as a type of instruction in the code segment that is referencing the label of an instruction, but the assembler has not yet encountered the definition of that instruction.

Pass 1: Assembler reads the entire source program and constructs a symbol table of names and labels used in the program, that is, name of data fields and programs labels and their relative location (offset) within the segment.

Pass 1 determines the amount of code to be generated for each instruction.

Pass 2: The assembler uses the symbol table that it constructed in Pass 1. Now it knows the length and relative of each data field and instruction, it can complete the object code for each instruction. It produces .OBJ (Object file), .LST (list file) and cross reference (.CRF) files.

## List three differences between Dynamic RAM and Static RAM. 3m Jun2008

List three differences between Dynamic RAM and Static RAM. 3m Jun2008

Static RAM

ü  SRAM uses transistor to store a single bit of data

ü  SRAM does not need periodic refreshment to maintain data

ü  SRAM’s structure is complex than DRAM

ü  SRAM are expensive as compared to DRAM

ü  SRAM are faster than DRAM

ü  SRAM are used in Cache memory

Dynamic RAM

ü  DRAM uses a separate capacitor to store each bit of data

ü  DRAM needs periodic refreshment to maintain the charge in the capacitors for data

ü  DRAM’s structure is simplex than SRAM

ü  DRAM’s are less expensive as compared to SRAM

ü  DRAM’s are slower than SRAM

ü  DRAM are used in Main memory

## Draw logic circuit for a converter that converts 4 bit binary input to its equivalent BCD number. 8m Jun2008

Draw logic circuit for a converter that converts 4 bit binary input to its equivalent BCD number. 8m Jun2008

A four bit number can be any number value between 0 to 15  i.e.  0 to F in Hexadecimal.

BCD is a number which is represented in binary as a decimal number hence it can have a max of 9 number value in the representation and the number ranging from 10 to 15 will need two digits and their will be common value 1 in all number from 10 to 15.

Truth Table: -

K map for O1: -

K map for O2: -

K map for O3: -

K map for O4: -

K map for O5: -

Logical and Block Diagram: -

Block Diagram for 4 bit to BCD conversion.