Monthly Archives: January 2015

Explain the process of handling an interrupt that occurs during a program? 9m jun2006

Explain the process of handling an interrupt that occurs during the execution of a program, with the help of an example. 9m jun2006   Interrupt Handling and Instruction Cycle  On the occurrence of an interrupt, an interrupt request (in the form of a signal) is issued to the CPU. The CPU on receipt of interrupt… Read More »

What is the significance of FAT? What are the limitations of FAT 16? 4m jun2006

What is the significance of FAT? What are the limitations of FAT 16?  4m jun2006 FAT The FAT maps the usage of data space of the disk. It contains information about the space used by each individual file, the unused disk space and the space that is unusable due to defects in the disk. Since… Read More »

Explain any five addressing modes used in an 8086 microprocessor, with the help of an example of each. 5m jun2006

Explain any five addressing modes used in an 8086 microprocessor, with the help of an example of each.    5m jun2006 The following tree shows the common addressing modes: In general not all of the above modes are used for all applications. However, some of the common areas where compilers of high-level languages use them are:… Read More »

Write an 8086 assembly language program that finds the largest, and the second largest number from a list of 10 numbers stored in the memory 6m Jun2006

Write an 8086 assembly language program that finds the largest, and the second largest number from a list of 10 numbers stored in the memory 6m Jun2006 To understand program for Largest in an array in detail Please Click this link below http://cssimplified.com/computer-organisation-and-assembly-language-programming/an-assembly-program-for-finding-the-largest-number-in-array-of-10-elements DATA SEGMENT ARR DB 5,3,7,1,9,2,6,8,4 LEN DW $-ARR LARGE DB ? SECOND… Read More »

Draw the logic diagram of a full adder. Create a 2-bit adder-subtractor circuit using the block diagram of the full adder 6m Jun2006

Draw the logic diagram of a full adder. Create a 2-bit adder-subtractor circuit using the block diagram of the full adder 6m Jun2006 A combinational circuit which performs addition of two bits is called a half adder, while the combinational circuit which performs arithmetic addition of three bits (the third bit is the previous carry bit)… Read More »

Explain the following: Parity bit, Floating point notation, Refresh rates in video controllers and an l/O channel 8m Jun2006

Explain the following with the help of an example or a diagram, whichever is appropriate:    8m jun2006 (i)                 Parity bit (ii)               Floating point notation (iii)             Refresh rates in video controllers (iv)             An l/O channel     Parity bit An error bit changes from 0 to 1 or 1 to 0. One of the simplest… Read More »

Simplify the following Boolean function in POS form using K-maps, also draw a logic diagram using only NAND gates 5m Dec2005

 Simplify the following boolean function in POS form using K-maps : F (A, B, C, D) = Σ (0, 2, 4, 5, 6, 8, 10, 13, 15) Also draw a logic diagram using only NAND gates.         5m Dec2005    K-Map for F is: Thus, the simplified equations for F (A, B, C, D) =… Read More »

Evaluate the effective address if addressing mode is Direct, Relative, Register indirect, Index with lndex register 6m Dec2005

An instruction is stored at location 500 with its address field at location 501. The address field has the value 300. A processor register R1 contains the number 100. Evaluate the effective address if the addressing mode of the instruction is   6m Dec2005                        … Read More »