Monthly Archives: January 2015


Explain the process of handling an interrupt that occurs during a program? 9m jun2006

Explain the process of handling an interrupt that occurs during the execution of a program, with the help of an example. 9m jun2006

 

Interrupt Handling and Instruction Cycle

 On the occurrence of an interrupt, an interrupt request (in the form of a signal) is issued to the CPU. The CPU on receipt of interrupt request suspends the operation of the currently executing program, saves the context of the currently executing program and starts executing the program which services that interrupt request. This program is also known as interrupt handler. After the interrupting condition/ device have been serviced the execution of original program is resumed.

Thus, an interrupt can be considered as the interruption of the execution of an ongoing user program. The execution of user program resumes as soon as the interrupt processing is completed. Therefore, the user program does not contain any code for interrupt handling. This job is to be performed by the processor and the operating system, which in turn is also responsible for suspending the execution of the user program, and later after interrupt handling, resumes the user program from the point of interruption.

Interrupt_Cycle

But when can a user program execution are interrupted?

It will not be desirable to interrupt a program while an instruction is getting executed and is in a state like instruction decode. The most desirable place for program interruption would be when it has completed the previous instruction and is about to start a new instruction. Figure 7 shows instruction execution cycle with interrupt cycle, where the interrupt condition is acknowledged. Please note that even interrupt service routine is also a program and after acknowledging interrupt the next instruction executed through instruction cycle is the first instruction of interrupt servicing routine.

In the interrupt cycle, the responsibility of the CPU/Processor is to check whether any interrupts have occurred checking the presence of the interrupt signal. In case no interrupt needs service, the processor proceeds to the next instruction of the current program.

 

In case an interrupt needs servicing then the interrupt is processed as per the following.

  •  Suspend the execution of current program and save its context.
  •  Set the Program counter to the starting address of the interrupt service routine of the interrupt acknowledged.
  •  The processor then executes the instructions in the interrupt-servicing program. The interrupt servicing programs are normally part of the operating system.
  •  After completing the interrupt servicing program the CPU can resume the program it has suspended in step 1 above.

What is the significance of FAT? What are the limitations of FAT 16? 4m jun2006

What is the significance of FAT? What are the limitations of FAT 16?  4m jun2006

FAT

The FAT maps the usage of data space of the disk. It contains information about the space used by each individual file, the unused disk space and the space that is unusable due to defects in the disk. Since FAT contains vital information, two copies of FAT are stored on the disk, so that in case one gets destroyed, the other can be used.

A FAT entry can contain any of the following:

  • unused cluster
  • reserved cluster
  • bad cluster
  • last cluster in file
  • next cluster number in the file.

The DOS file system maintains a table of pointers called FAT (File allocation table) which consists of an array of 16-bit values. There is one entry in the FAT for each cluster in the file area, i.e., each entry of the FAT (except the two) corresponds to one cluster of disk space. If the value in the FAT entry doesn’t mark an unused, reserved or defective cluster, then the cluster corresponding to the FAT entry is part of a file and the value in the FAT entry would indicate the next cluster in the file.

The first two entries (0 & 1) in FAT are reserved for use by the operating system.

Therefore, the cluster number 2 corresponds to the first cluster in the data space of the disk. Prior to any data being written on to the disk, the FAT entries are all set to zero indicating a ‘free’ cluster .The FAT chain for a file ends with the hexadecimal value, i.e., FFFF. The FAT structure can be shown as in Figure 2 below.

FAT_Structure

 Limitation of FAT16: The DOS designers decided to use clusters with at least four sectors in them (thus a cluster size of at least 2KB) for all FAT16 hard disks. That size suffices for any hard disk with less than a 128MB total capacity. The largest logical disk drives that DOS can handle comfortably have capacities up to 2GB. For such a large volume, the cluster size is 32KB. This means that even if a file contains only a single byte of data, writing it to the disk uses one entire 32KB region of the disk, making that area unavailable for any other file’s data storage.

The most recent solution to these large-disk problems was introduced by Microsoft in its OSR2 release of Windows 95 and it was named FAT32. The cluster entry for FAT32 uses 32-bit numbers. The minimum size for a FAT32 volume is 512MB.

Microsoft has reserved the top four bits of every cluster number in a FAT32 file allocation table. That means there are only 28-bits for the cluster number, so the maximum cluster number possible is 268,435,456.

Explain any five addressing modes used in an 8086 microprocessor, with the help of an example of each. 5m jun2006

Explain any five addressing modes used in an 8086 microprocessor, with the help of an example of each.    5m jun2006

The following tree shows the common addressing modes:

Common_Addressing_Modes

In general not all of the above modes are used for all applications. However, some of the common areas where compilers of high-level languages use them are:

Use_of_Addressing_Modes

Immediate Addressing

When an operand is interpreted as an immediate value, e.g. LOAD IMMEDIATE 7, it is the actual value 7 that is put in the CPU register. In this mode the operand is the data in operand address field of the instruction. Since there is no address field at all, and hence no additional memory accesses are required for executing this instruction. In other words, in this addressing scheme, the actual operand D is A, the content of the operand field: i.e. D = A. The effective address in this case is not defined.

 Addressing_Immediate

Direct Addressing

In this scheme the operand field of the instruction specifies the direct address of the intended operand, e.g., if the instruction LOAD 500 uses direct addressing, then it will result in loading the contents of memory cell 500 into the CPU register. In this mode the intended operand is the address of the data in operation. For example, if memory cell 500 contains 7, as in the diagram below, then the value 7 will be loaded to CPU register.

Addressing_Direct

Indirect Addressing

In this scheme the operand field of the instruction specifies the address of the address of intended operand, e.g., if the instruction LOAD I 500 uses indirect addressing scheme, and contains a value 50A, and memory location 50A contains 7, then the value 7 will get loaded in the CPU register.

Addressing_Indirect

Register Addressing

When operands are taken from register(s), implicitly or explicitly, it is called register addressing. These operands are called register operands. If operands are from memory locations, they are called memory operands. In this scheme, a register address is specified in the instruction. That register contains the operand. It is conceptually similar to direct addressing scheme except that the register name or number is substituted for memory address.

Addressing_Register

Register Indirect Addressing

In this addressing scheme, the operand is data in the memory pointed to by a register.

In other words, the operand field specifies a register that contains the address of the operand that is stored in memory. This is almost same as indirect addressing scheme except it is much faster than indirect addressing that requires two memory accesses.

 Addressing_Register_Indirect

Stack Addressing

In this addressing scheme, the operand is implied as top of stack. It is not explicit, but implied. It uses a CPU Register called Stack Pointer (SP). The SP points to the top of the stack i.e. to the memory location where the last value was pushed. A stack provides a sort-of indirect addressing and indexed addressing. This is not a very common addressing scheme. The operand is found on the top of a stack. In some machines the top two elements of stack and top of stack pointer is kept in the CPU registers, while the rest of the elements may reside in the memory.

Addressing_Stack

 

 

What is the sequence of micro-operations required to fetch an instruction? 5m jun2006

Solved Answer can be found on this link http://cssimplified.com/assignments/write-and-explain-the-sequence-of-micro-operations-that-are-required-to-fetch-and-execute-this-instruction-ignou-mca-assignment-2014-15

 

Assume a computer has 32 words RAM each having a word of 16 bits and a cache memory of 4 blocks, with each block having 16 bits. Where can we find a main memory address 21 in the cache (if it exists) if

(i) Set associative mapping is used?

(ii) Direct mapping is used?

(iii) Associative mapping is used?

Explain your answers with the help of a diagram in each case.          10m jun2006

 

Similar Solved Answer can be found on this link http://cssimplified.com/assignments/a-computer-has-512-words-ram-with-a-word-size-of-32-bits-and-a-cache-memory-of-8-blocks-with-block-size-of-64-bits-ignou-mca-assignment-2014-15

 

Write an 8086 assembly language program that finds the largest, and the second largest number from a list of 10 numbers stored in the memory 6m Jun2006

Write an 8086 assembly language program that finds the largest, and the second largest number from a list of 10 numbers stored in the memory 6m Jun2006

To understand program for Largest in an array in detail Please Click this link below http://cssimplified.com/computer-organisation-and-assembly-language-programming/an-assembly-program-for-finding-the-largest-number-in-array-of-10-elements

DATA SEGMENT
ARR DB 5,3,7,1,9,2,6,8,4
LEN DW $-ARR
LARGE DB ?
SECOND DB ?
DATA ENDS

CODE SEGMENT
ASSUME DS:DATA CS:CODE
START:
MOV AX,DATA
MOV DS,AX

LEA SI,ARR
MOV AL,ARR[SI]
MOV LARGE,AL

MOV CX,LEN
REPEAT1:
MOV AL,ARR[SI]
CMP LARGE,AL
JG NOCHANGE

MOV LARGE,AL
NOCHANGE:
INC SI
LOOP REPEAT1

LEA SI,ARR
MOV AL,ARR[SI]
MOV SECOND,AL

MOV CX,LEN
REPEAT2:
MOV AL,ARR[SI]
CMP SECOND,AL
JG SKIP

CMP LARGE,AL
JLE SKIP

MOV SECOND,AL
SKIP:
INC SI
LOOP REPEAT2

MOV AH,4CH
INT 21H
CODE ENDS
END START

Program code: -

 

 DATA SEGMENT
 
ARR DB 5,3,7,1,9,2,6,8,4
LEN DW $-ARR
LARGE DB ? 
SECOND DB ?
DATA ENDS
 
CODE SEGMENT 
ASSUME DS:DATA CS:CODE
START:
MOV AX,DATA
MOV DS,AX
 
LEA SI,ARR
MOV AL,ARR[SI]
MOV LARGE,AL
 
MOV CX,LEN
REPEAT1: 
MOV AL,ARR[SI]
CMP LARGE,AL
JG NOCHANGE
 
MOV LARGE,AL
NOCHANGE:
INC SI
LOOP REPEAT1 
 
LEA SI,ARR
MOV AL,ARR[SI]
MOV SECOND,AL
 
MOV CX,LEN
REPEAT2: 
MOV AL,ARR[SI]
CMP SECOND,AL
JG SKIP
 
CMP LARGE,AL
JLE SKIP
 
MOV SECOND,AL
SKIP:
INC SI
LOOP REPEAT2 
 
MOV AH,4CH
INT 21H 
CODE ENDS
END START

 

Screen shots: -

Asm_program_Second_Largest_in_Array

Before Execution: -

Asm_program_Second_Largest_in_Array_OP1

After Execution: -

Asm_program_Second_Largest_in_Array_OP2

Draw the logic diagram of a full adder. Create a 2-bit adder-subtractor circuit using the block diagram of the full adder 6m Jun2006

Draw the logic diagram of a full adder. Create a 2-bit adder-subtractor circuit using the block diagram of the full adder 6m Jun2006

A combinational circuit which performs addition of two bits is called a half adder, while the combinational circuit which performs arithmetic addition of three bits (the third bit is the previous carry bit) is called a full adder.

Truth Table: -

Full_Adder_Truth_Table

 

Logical and Block Diagram: -

Full_Adder

K map for Carry: -

Kmap003
K map for Sum: -

Kmap004

Adder – subtractor

The subtraction operation on binary numbers can be achieved by sequence of addition operations only i.e. to perform subtraction, A-B; we can find 2’s complement of B. This can be calculated using 1’s complemented & then adding 1 to it. Thus, a common circuit can perform the addition and subtraction operation. A 2-bit adder- subtraction circuit is shown in figure.

2-bit Adder – subtractor: -

Adder_Subtr_2_bit

 

                      Block Diagram

Explain the following: Parity bit, Floating point notation, Refresh rates in video controllers and an l/O channel 8m Jun2006

Explain the following with the help of an example or a diagram, whichever is appropriate:    8m jun2006

(i)                 Parity bit

(ii)               Floating point notation

(iii)             Refresh rates in video controllers

(iv)             An l/O channel

 

 

Parity bit

An error bit changes from 0 to 1 or 1 to 0. One of the simplest error detection codes is called parity bit.

Parity bit: – A parity bit is an error detection bit added to binary data such that it makes the total number of 1’s in the data either odd or even. For example, in a seven bit data 0110101 an 8th bit, which is a parity bit, may be added. If the added parity bit is even parity bit then the value of this parity bit should be zero, as already four 1’s exists in the 7-bit number. If we are adding an odd parity bit then it will be 1, since we already have four 1 bits in the number and on adding 8th bit (which is a parity bit) as 1 we are making total number of 1’s in the number (which now includes parity bit also) as 5, an odd number.

Similarly in data 0010101

Parity bit for even parity is 1

Parity bit for odd parity is 0

 

Floating point notation

Floating-point number representation consists of two parts. The first part of the number is a signed fixed-point number, which is termed as mantissa, and the second part specifies the decimal or binary point position and is termed as an Exponent. The mantissa can be an integer or a fraction. Please note that the position of decimal or binary point is assumed and it is not a physical point, therefore, wherever we are representing a point it is only the assumed position.

The following figure shows a format of a 16-bit and 32-bit floating-point number.

 precision

Refresh rates in video controllers

A special circuit called the Video Controller scans the video memory one row at a time and reads data value at each address sending the data out in a serial data stream.This data is displayed by a process called Scanning where the electron beam is swept across the screen one-line-at-a-time and left-to-right. This is controlled by a vertical and a horizontal field generated by electromagnets — one moving the beam horizontally and another vertically.

 

An I/O channel   

I/O channels – an independent processor for Input/Output

The I/O channel represents an extension of the DMA concept. An I/O channel has the ability to execute I/O instructions, which gives complete control over the I/O operation. With such devices, the CPU does not execute I/O instructions. Such instructions are stored in the main memory to be executed by a special-purpose processor in the I/O channel itself. Thus, the CPU initiates an I/O transfer by instructing the I/O channel to execute a program in memory.

Simplify the following Boolean function in POS form using K-maps, also draw a logic diagram using only NAND gates 5m Dec2005

 Simplify the following boolean function in POS form using K-maps :

F (A, B, C, D) = Σ (0, 2, 4, 5, 6, 8, 10, 13, 15)

Also draw a logic diagram using only NAND gates.         5m Dec2005

  

K-Map for F is:

Kmap002

Thus, the simplified equations for F (A, B, C, D) = Σ (0, 2, 4, 5, 6, 8, 10, 13, 15)

are:

F = (|A+|B+D) (B+|D) (|C+|D)

Logic diagram:-

Logic_Diag01

 

Logic diagram using only NAND gates:-

Logic_Diag02

 Assume a compuier having 64 word RAM and cache memory of 8 blocks. Where can we find the main memory location 26 in cache jf

(i) Associative mapping is used;

(ii) Direct rnapping is used;

(iii) 2-way set associative (2 blocks per set) mapping is used.

Assume 1 word = 16 bits and block size = 32 bits   Make suitable assumptions if any 5m Dec2005

 

Solved answer can be found on this link http://cssimplified.com/assignments/a-computer-has-512-words-ram-with-a-word-size-of-32-bits-and-a-cache-memory-of-8-blocks-with-block-size-of-64-bits-ignou-mca-assignment-2014-15

Evaluate the effective address if addressing mode is Direct, Relative, Register indirect, Index with lndex register 6m Dec2005

An instruction is stored at location 500 with its address field at location 501. The address field has the value 300. A processor register R1 contains the number 100. Evaluate the effective address if the addressing mode of the instruction is   6m Dec2005                        

(i) Direct                                               

(ii) Relative                                                                               

(iii) Register indirect      

(iv) Index with R1 as lndex register

Make suitable assumptions if any

An instruction is stored in memory at an address designated by the symbol W. The address field of the instruction (stored at W +1) is designated by the symbol Y. The operand used during the execution of the instruction is stored at an address symbolized by z. An index register contains the value X. State how Z is calculated from other addresses if the addressing of the instruction is

  1. Direct
  2. Indirect
  3. Relative
  4. Indexed

Evaluate=EA_1

 

An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode of the instruction is   6m Dec2005

(i) Direct

(ii) Relative

(iii) Register indirect

(iv) Index with R1 as lndex register

Evaluate=EA_2

Similarly

Evaluate=EA_3