Monthly Archives: August 2015


Use a Karnaugh’s map to design if the output bit is 0 if the first and fourth input are same else it is 1 for 4 input bits – IGNOU MCA Assignment 2015 – 16

MASTER OF COMPUTER APPLICATIONS

Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA(I)/012/Assignment/15-16
Maximum Marks : 100
Weightage : 25%

 

Use a Karnaugh’s map to design a circuit that takes four input bits and produces one output bit. The output bit is 0 if the first and fourth input are same else it is 1.

 

Before Designing we should know inputs which is 4

That means 24 = 16 Combinations of outputs

Inputs are represented as ABCD

Output is represented by F and some times termed as Function

 

Decimal

A

B

C

D

F (Function)

0

0

0

0

0

 

1

0

0

0

1

 

2

0

0

1

0

 

3

0

0

1

1

 

4

0

1

0

0

 

5

0

1

0

1

 

6

0

1

1

0

 

7

0

1

1

1

 

8

1

0

0

0

 

9

1

0

0

1

 

10

1

0

1

0

 

11

1

0

1

1

 

12

1

1

0

0

 

13

1

1

0

1

 

14

1

1

1

0

 

15

1

1

1

1

 

Before proceeding we should know what odd parity is for ABCD inputs?

There are two types of parity even parity and odd parity

The parity is 0 or 1 depending upon total numbers of 1s

If count of 1s is even number then even parity = 0 and odd parity = 1

Similarly If count of 1s is odd number then even parity = 1 and odd parity = 0

After Finding out odd parity for ABCD inputs

We have Table as:-

 

Decimal

A

B

C

D

F (Function)

0

0

0

0

0

0

1

0

0

0

1

1

2

0

0

1

0

0

3

0

0

1

1

1

4

0

1

0

0

0

5

0

1

0

1

1

6

0

1

1

0

0

7

0

1

1

1

1

8

1

0

0

0

1

9

1

0

0

1

0

10

1

0

1

0

1

11

1

0

1

1

0

12

1

1

0

0

1

13

1

1

0

1

0

14

1

1

1

0

1

15

1

1

1

1

0

 

It’s can also be written as F =Σ (1, 3, 5, 7, 8, 10, 12, 14)

Only the decimal number where we find 1’s is shown in the Bracket.

Final Equation:-

Kmap012

An 8 bit data 01101101 after transmission is received as 01001101. Explain how SEC code will detect and correct – IGNOU MCA Assignment 2015 – 16

MASTER OF COMPUTER APPLICATIONS

Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA(I)/012/Assignment/15-16
Maximum Marks : 100
Weightage : 25%

 

An 8 bit data 01101101 after transmission is received as 01001101. Explain how SEC code will detect and correct this problem.

 

SEC means Single Error Correction

This if found in Hamming Error Correction Code

First find out the number parity bits in SEC Code

Formula:

2i – 1 >= N + i

where

i = number of parity bits in SEC Code

N = number of  bits in Data Word

 

In this case

N=8

i=?

So,

2i – 1 >= N + I                at  i=3

 

23 – 1 >= 8 + 3

7 >= 11 (Not True)

So,

2i – 1 >= N + I                at  i=4

 

24 – 1 >= 8 + 4

15 >= 12 (True)

Condition Satisfied.

 

 

Coorection bits (parity bits) are 4.

 

Parity bits are placed at 20  21  22  2                    i.e.   1 2 4 8          respectively

 

P1

P2

D1

P3

D2

D3

D4

P4

D5

D6

D7

D8

1

2

3

4

5

6

7

8

9

10

11

12

?

?

?

?

 

D1 D2 D3 D4 D5 D6 D7 D8 are the data sent and recd.

 

Before sending calculate Parity of  Data to be sent.

 

P1

P2

D1

P3

D2

D3

D4

P4

D5

D6

D7

D8

1

2

3

4

5

6

7

8

9

10

11

12

?

?

0

?

1

1

0

?

1

1

0

1

 

P1     =      ?        0        1        0        1        0

(Positions)  1        3        5        7        9        11

 

Starting Point will be after Parity position P1 i.e 2 and Take 1 Skip 1 till the end of table data.

We get 01010

It’s even parity will be 0

 

P2     =      ?        0        1        0        1        0

(Positions)  2        3        6        7        10      11

 

Starting Point will be after Parity position P2 i.e 3 and Take 2 Skip 2 till the end of table data.

We get 01010

It’s even parity will be 0

 

P3     =      ?        1        1        0        1

(Positions)  4        5        6        7        12

 

Starting Point will be after Parity position P3 i.e 4 and Take 4 Skip 4 till the end of table data.

We get 1101

It’s even parity will be 1

 

P3     =      ?        1        1        0        1

(Positions)  8        9        10      11      12

 

Starting Point will be after Parity position P3 i.e 4 and Take 8 Skip 8 till the end of table data. (Note:- data ends before taking 8 elements.)

We get 1101

It’s even parity will be 1

 

We found all parity bits, we will fill in the table:-

 

P1

P2

D1

P3

D2

D3

D4

P4

D5

D6

D7

D8

1

2

3

4

5

6

7

8

9

10

11

12

0

0

0

1

1

1

0

1

1

1

0

1

 

Assuming all parity sent correctly

The 8-bit Sent Data = 0110 1101

The 8-bit Sent Data = 0100 1101

 

Check with parity bits, before that Create a new parity bit with new data

 

P1=   D1     D2     D4     D5     D7 =   01010         even parity will be 0   – correct

P2=   D1     D3     D4     D6     D7=   00010         even parity will be 1   - incorrect

P3=   D2     D3     D4     D8           =    1001         even parity will be 0   - incorrect

P4=   D5     D6     D7     D8           =    1101         even parity will be 1   – correct

 

After Checking

We find that common data bit numbers are D3 & D4

But D4 is also present in P1that means error has been occurred in D3 only.

 By this we dectect error in D3 and Correct it by replacing it by 0 to 1.

Design a two bit counter (a sequential circuit) that counts from 00 to 10 only – IGNOU MCA Assignment 2015 – 16

MASTER OF COMPUTER APPLICATIONS

Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA(I)/012/Assignment/15-16
Maximum Marks : 100
Weightage : 25%

Design a two bit counter (a sequential circuit) that counts from 00 to 10 only. Thus, the counter states are 00, 01, 10, 00, 01,…. You should show the state table, state diagram, the k-map for circuit design and logic diagram of the resultant design using D flip-flop or J-K flip flop.

 

Solution : 

A sequential circuit is specified by a time sequence of external inputs, external outputs and internal flip-flop binary states. Thus firstly, a state table and state diagram is used to describe behaviour of the circuit.

Decade_Counter_D_Flip_Flop_Table_02 

Present State

 

Input

Next State

Flip-Flops Inputs

A

 

B

X

A

 

B

DA

DB

0

 

0

0

0

0

0

0

0

 

0

1

0

1

0

1

0

 

1

0

0

1

0

1

0

 

1

1

1

0

1

0

1

0

0

 

1

0

1

0

1

0

1

 

1

1

0

0

1

 

1

0

1

1

0

0

1

 

1

1

0

0

0

1

 

There are 2 flip-flop inputs for counter i.e. A, B. The next state of flip-flop is given in the table. DA indicates the flip flop input corresponding to flip-flop-A. This counter requires 2-flip-flops.

From this the flip flop input equations are simplified using K-Maps as shown below.

 

K-Map for DA is:

Kmap010

K-Map for DB is:

Kmap011

Thus, the simplified input equations for Counter are:

DA = |ABX + A|B|X

DB = |A|BX + |AB|X + ABX

Down_Counter_D_Flip_Flop_02

The logic circuit can be made with 2 D flip flops, 2 OR gates & 4 AND gates.

Represent (124.0625)10 using IEEE 754 single and double precision representations – IGNOU MCA Assignment 2015 – 16

MASTER OF COMPUTER APPLICATIONS
Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA (2)/012/Assign /2015-16
Maximum Marks : 100
Weightage : 25%

 

Explain the double precision floating point IEEE 754 representation. Represent the number (124.0625)10 using IEEE 754 single precision and double precision representations. 

precision

Single Precision

 

S stands for Sign (white color)

E stands for Exponent (yellow color)

N stands for Number (also called Mantissa or Significand) (green color)

 

0this Sign bit (1 bit)

1st to 8this Exponent bits (7 bits)

9thto 31this Exponent bits (24 bits)

Double Precision

 

S stands for Sign (white color)

E stands for Exponent (yellow color)

N stands for Number (also called Mantissa or Significand) (green color)

 

0this Sign bit (1 bit)

1st to 11this Exponent bits (10 bits)

12thto 63this Exponent bits (53 bits)

 

First of all to represent we have (63.125)10 using IEEE 754

Since number is a positive number

Sign bit is: 0

0

Now let’s work on Mantissa part

Convert 124 into binary form i.e 1111100

Remaining is fraction part 0.0625

Now we multiply fraction value with 2 till we get whole number 1 at the end.

Fraction_Precision_02

We reach 1 so we stop

Write number from top to bottom

We get 0.0625 = 0001

Number (124.0625)10 = (1111100.0001)2

Convert Binary number to Exponent Form

1111100.0001 Will be 1.1111000001 * 26

Discard 1.

Take 1111000001 as Significand

Significand number = (1111000001)2

Significand bits are:

1 1 1 1 0 0 0 0 0 1

 

Fill the Significand in the beginning

Rest all fills it with 0’s

We will have

Significand bits are:

1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

 

+6 is the Exponent

So we have to subtract it with 127

Exponent = 127+6=132

Exponent number (132)10 = (10000100)2

Discard overflow bit

Exponent bits are:

0 0 0 0 1 0 0

 

Note: we have to discard overflow bit since we have only 7 bits

 

 

For Double Precision Only Exponent

+6 is the Exponent

So we have to subtract it with 1023

Exponent = 1023+6=1029

Exponent number (1029)10 = (10000000101)2

Discard overflow bit

Exponent bits are:

0 0 0 0 0 0 0 1 0 1

Note: we have to discard overflow bit since we have only 11 bits

Significand bits are:

1 1 1 1 0 0 0  0  0 1

Significand will only have a change in terms of Zero’s which are added at the end.

For single precision 23-10=13 Zero’s

For double precision 53-10=43 Zero’s

 

A RAM has a capacity of 8192K having the word size of 16 bits and supports byte addresses only – IGNOU MCA Assignment 2015 – 16

MASTER OF COMPUTER APPLICATIONS

Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA (2)/012/Assign /2014-15
Maximum Marks : 100
Weightage : 25%

A RAM has a capacity of 8192K having the word size of 16 bits and supports byte addresses only – IGNOU MCA Assignment 2015 – 16

Explanation of Concept:

RAM32x4

 

A 32 × 4 RAM means that RAM has 32 words,

5 address lines (25 = 32), and 4 bit data word size.

We can represent a RAM using 2A×D,

Where

A-> Number of address lines

D -> Number of Data lines

The 32 × 4 RAM circuit where 5 × 32 bit decoder is used

The 4 bit data input come from input buffer

The 4-bit data output is stored in output buffer

 

A RAM has a capacity of 8192K having the word size of 16 bits and supports byte addresses only – IGNOU MCA Assignment 2015 – 16

 

 

A RAM has a capacity of 8192K having the word size of 16 bits and supports byte addresses only.

 

(i)                How many data input and output lines does this RAM need? Explain your answer.

Ans:  Data input and Data output lines are equal and of word size, Hence Ram will need 16 Data lines

 

(ii)             How many address lines will be needed for this RAM? Explain.

Ans:  Convert 8192K to  2× (D/2)  format supports byte addresses only

8192K/8 

= (8192 * 1024) / 8 

= (213 * 210) / 23 

=223-3

=213

We can represent a RAM using 2A × (D/2) = 213 × (16/2) RAM Hence Address lines are 13 Address lines.

Draw a diagram address mapping of RAM & Cache – IGNOU MCA Assignment 2015 – 16

MASTER OF COMPUTER APPLICATIONS

Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA(I)/012/Assignment/15-16
Maximum Marks : 100
Weightage : 25%

 

A computer has 1MB RAM and has word size of 16 bits. It has cache memory having 16 blocks with a block size of 32 bits. Explain how a main memory address will be mapped to a cache address, if

(i) Direct cache mapping is used

(ii) Associative cache mapping is used

(iii) Two way set associative mapping scheme is used.

Given:

Main memory Size = 1 MB (RAM)

Convert it to Words if word size is 16 bits 

Main memory Size = 65536 Words

Main Memory word size = 16 bits

Cache Memory Size = 16 Blocks

Cache Memory Block size = 32 bits

 

 

⇒1 Block of Cache = 2 Words of RAM

Assume Memory location address 520 is equivalent to Block address 260.

⇒ Total number of possible Blocks in Main Memory = 65536 /2 = 32768 blocks

Mapping03

Associative Mapping:

The block can be anywhere in the cache.

Direct Mapping:

Size of Cache = 16 blocks

Location of Block 260 in Cache = 260 modulo 16 = 4

2 Way set associative mapping:

Number of blocks in a set = 2

Number of sets = Size of Cache in blocks / Number of blocks in a set

= 32768  / 2 = 16384

Block 260 will be located anywhere in (260 modulo 8) set, that is set 4.

Explain the term FAT in the context of disk operating system. What will be the size of a disk and it’s FAT? – IGNOU MCA Assignment 2015 – 16

MASTER OF COMPUTER APPLICATIONS

Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA(I)/012/Assignment/15-16
Maximum Marks : 100
Weightage : 25%

Explain the term FAT in the context of disk operating system. What will be the size of a disk and it’s FAT, if a disk has 64 tracks with each track having 16 sectors and size of each sector is 512 byte? You may take the cluster size as 4 sectors.

 

Given:

Disk has 64 tracks

Track has 16 sectors

Sector is 512 byte (0.5 KB)

Cluster size as 4 sectors

 

Find:

            Disk Size (or Disk Capacity)?

            It’s FAT (or FAT entries)?

 

Track Size (in KB) = No. of Sector x No. of Btyes

 

= 16 * 0.5 KB

 

= 8 KB

 

Cluster Size (in KB) = No. of Track x No. of Sector

 

= 64 * 8 KB

 

= 512 KB

 

Disk Size (in KB) = No. of Cluster x No. of Track

 

= 4 * 512 KB

 

= 2048 KB

 

=2MB

 

Disk Size (or Disk Capacity) = 2 MB

 

Note: FAT contains vital information; two copies of FAT are stored on the disk, so that in case one gets destroyed, the other can be used

 

It’s FAT (or FAT entries) = Disk Size (or Disk Capacity) / Cluster Size

 

= (2 * 1024 * 1024) / (2 * 1024)

 

= (2 * 1024 * 1024) / (2 * 1024)

 

= 1024 No. of entries

 

Note: FAT contains vital information; two copies of FAT are stored on the disk, so that in case one gets destroyed, the other can be used (Acutual entries = 1024 entries / 2 = 512 entries).

Assume that a new machine has been developed. Give justification of the selection of every addressing mode? – IGNOU MCA Assignment 2015 – 16

MASTER OF COMPUTER APPLICATIONS

Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA(I)/012/Assignment/15-16
Maximum Marks : 100
Weightage : 25%

A hypothetical machine has 22 registers. Out of these 6 registers are used as segment registers. Assume that the machine uses segment registers to find physical address in the similar way as is done in 8086 processor. Remaining 16 registers are general purpose registers. All the registers and memory word for the machine are of 16 bits. The machine has 1 M Word RAM. An instruction of the machine is of 32 bits which includes opcode – 5 bits, addressing mode specification – 3 bits and remaining bits for specifying the operand addresses.

 Each instruction contains at most two operand addresses – at most one memory operand and remaining register operand(s). What would be the size of memory address, if direct addressing is used? What would be the size of the direct register operand? The machine is to be used for calculations involving arrays and floating point numbers. Design five different types of addressing modes for this machine. Give justification of the selection of every addressing mode.

Total general purpose registers = 32

All Register equal size = 16 bits

Registers used as stack for subroutine calls = 16

Main memory = 1 M Word

Memory word size = 16 bits

Instructions size = one memory word = 16 bits

Opcode = 5 bits

Addressing mode = 3 bits

Remaining bits = operand addresses

 

Please note the following points:

  • The opcode size is 5 bits. So, in general it will have 25 = 16 operations.
  • There is three operand address machine.
  • There are two bits for addressing modes. Therefore, there are 23 = 6 different addressing modes possible for this machine.
  • The last field (8 – 32 bits = 24 bits) here is the operands or the addresses of operands field.

Instruction_Format_07 

Each instruction contains at most two operand addresses – at most one memory operand and remaining register operand(s). Hence one register operand has to be involved in all Addressing modes, so we have to use first operand as Register for all modes and this will be common for all.

Instruction_Format_08

IMMEDIATE addressing mode:

Instruction_Format_08 

ADD R 12 13                              R = 12 + 13

 

In case of immediate operand the maximum size of the unsigned operand would be 210

 

DIRECT addressing mode:

 

Instruction_Format_09

 

ADD R A B                                 R = A + B

 

In case it is an address of operand in memory, then the maximum physical memory size supported by this machine is 210 = 1 KB.

 

REGISTER addressing mode:

Instruction_Format_10

 

ADD R1 RR3                             R1 = R2 + R3

 

There are 64 general purpose registers. Therefore, there is 64 = 26 (6-bits for Register address)

 

REGISTER INDIRECT addressing mode:

Instruction_Format_11

 

ADD R1 R2 R3                              R1 = R+ R3

ADD R1 (R2 ) (R3 )                       R1 = (R2 ) + (R3 )

ADD R A B                                 R = A + B

 

There are 64 general purpose registers. Therefore, there is 64 = 26(6-bits for Register address).

Write and explain the sequence of micro-operations that are required to fetch and execute this instruction? – IGNOU MCA Assignment 2015 – 16

MASTER OF COMPUTER APPLICATIONS

Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA(I)/012/Assignment/15-16
Maximum Marks : 100
Weightage : 25%

 

Assume that the machine as stated in part (a) has named 5 of its general purpose registers based on their possible role in instruction execution as Program Counter (PC), Accumulator (AC), Memory Address Register (MAR), Instruction Register (IR) , Data Register (DR) and Flag registers (FR). To execute an instruction of the machine that has a direct memory operand and a register operand, the memory operand is first brought into the DR register and the register operand is transferred to AC register. The result of the operation is stored in the AC register. One of the instructions of the machine is given below:

ADD R1, X // this instruction adds the operand stored in

Register R1 and memory location X. The result is stored in the AC register.

Write and explain the sequence of micro-operations that are required to fetch and execute this instruction. Make and state suitable assumptions, if any.

STORE memAddress    // this instruction result in storage of the content of AC register into the memory location specified by memAddress.

Write and explain the sequence of micro-operations that are required to fetch and execute this instruction Make and state suitable assumptions, if any.

 

The instruction execution using the micro-operations requires:

  • Instruction fetch: fetching the instruction from the memory.
  • Instruction decode: decode the instruction.
  • Operand address calculation: find out the effective address of the operands.
  • Execution: execute the instruction.
  • Interrupt Acknowledge: perform an interrupt acknowledge cycle if an interrupt request is pending.Seq_Micro_Operations_01 

    Instruction fetch:

    Transfer the address of PC to MAR. (Register Transfer) MAR ß PC
    MAR puts its contents on the address bus for main and issues a memory read signal. The word so read is placed on the data bus where it is accepted by the Data register.The PC is incremented by one memory word length to point to the next instruction in sequence. DR ß (MAR), 

    PCß PC +1

    The instruction is transferred from data register to the Instruction register processing. IR ß DR

     

    Instruction Decode: The Control Unit determines the operation that is to be performed and the addressing mode of the data.

     

    Operand Address Calculation: (In case of direct addressing)

    Transfer the address portion of instruction is the direct address so no further calculation needed. IR (Address) and DR (Address) contain the Effective address.

     

    Operand Address Calculation: (In case of indirect addressing)

    Transfer the address bits of instruction to the MAR. This transfer can be achieved using DR, as DR and IR at this point of time contain the same value. (Register Transfer) MAR ß DR (Address)
    Perform a memory read operation as done in fetch cycle and the desired address of the operand is obtained in the DR. (Memory Read) DR ß (MAR)
    Transfer the address part so obtained in DR as the address part of instruction. (Register Transfer) Thus, the indirect address is now converted to direct address or effective address. IR (Address) ß DR (Address)

     

    Execution:

    Transfer the address portion of the instruction to the MAR. (MemAddress transfer) MAR ß MemAddress
    Store the AC register to Memory Address in MAR.   (MAR) ß AC

     

    Interrupt Processing:

    Transfer the contents of PC to DR DR ß PC
    Place the address of location, where the return address is to be saved, into MAR. MAR ß Address of location for saving return address.
    Store the contents of PC in the memory using DR and MAR. (Memory write) Transfer the address of the first instruction of interrupt servicing routine to the PC. (MAR) ßDRPC ß address of the first instruction interrupt service programs

What will be the values of select inputs, carry-in input and result of operation if the following micro-operations are performed? – IGNOU MCA Assignment 2015 – 16

MASTER OF COMPUTER APPLICATIONS
Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA (2)/012/Assign /2014-15
Maximum Marks : 100
Weightage : 25%

 

Assume that you have a machine as shown in section 3.2.2 of Block 3 having the micro-operations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8 bit registers and contains 1010 0011 and 1100 1011 respectively. What will be the values of select inputs, carry-in input and result of operation (including carry out bit) if the following micro-operations are performed? (For each micro-operation you may assume the initial value of R1 and R2 as given above).

(i) Subtraction of R1 and R2

(ii) AND of R1 and R2

(iii) Shift right R2 twice

(iv) Add of R1 and R2 with carry

 

(i) Subtraction of R1 and R2

 

S3

S2

S1

S0

Ci

F

Micro-operation

Name

0

0

1

0

1

F=x+( |y+1)

R ß R1 – R2

Subtraction

 

 

1 1 0 0 1 0 1 1

R2=

0 0 1 1 0 1 0 0
+ 1
0 0 1 1 0 1 0 1

|R2=

 

 

 

1 0 1 0 0 0 1 1
0 0 1 1 0 1 0 1
1 1 0 1 1 0 0 0

 

S3

S2

S1

S0

Ci

F

Micro-operation

Name

Value of Result R

0

0

1

0

1

F=x+( |y+1)

R ß R1 – R2

Subtraction

1101 1000

No Carry Out Occurred.

Micro-Operations_05

(ii) AND of R1 and R2 

S3

S2

S1

S0

Ci

F

Micro-operation

Name

0

1

0

0

-

F=x.y

R ß R1 ^ R2

AND

 

1 0 1 0 0 0 1 1
1 1 0 0 1 0 1 1
1 0 0 0 0 0 1 1

 

S3

S2

S1

S0

Ci

F

Micro-operation

Name

Value of Result R

0

1

0

0

-

F=x.y

R ß R1 ^ R2

AND

1000 0011

No Carry Out Occurred.

 Micro-Operation_06

(iii) Shift right R1 twice

S3

S2

S1

S0

Ci

F

Micro-operation

Name

1

1

-

-

-

F=Shr(y)

R ß Shr(R1)

Shift right

Shr(y) Function applied Twice on R1

1 0 1 0 0 0 1 1
1 1 0 1 0 0 0 1
1 1 1 0 1 0 0 0

S3

S2

S1

S0

Ci

F

Micro-operation

Name

Value of Result R

1

1

-

-

-

F=Shr(y)

R ß Shr(R1)

Shift right

1110 1000

No Carry Out Occurred.

Micro-Operation_07

(iv) Add of R1 and R2 with carry

S3

S2

S1

S0

Ci

F

Micro-operation

Name

0

0

0

1

1

F=x+y+1

R ß R1 + R2+1

Add with carry

 

1 0 1 0 0 0 1 1
1 1 0 0 1 0 1 1
1
0 1 1 0 1 1 1 1

Cout =                                 1

S3

S2

S1

S0

Ci

F

Micro-operation

Name

Value of Result R

0

0

0

1

1

F=x+y+1

R ß R1 + R2+1

Add with carry

1  0110  1111

Carry Out has occurred.

Micro-Operation_08